On average, the proposed method was able to remove 25.1% more gates. A huge improvement was achieved especially for the arithmetic circuits. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. When applied appropriately, this approach can mitigate the problem of scalability of representation. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. To overcome this issue, we propose to apply the concept of local resynthesis in this work. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. Unfortunately, we are facing another problem-scalability of representation. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. The results are assessed considering a benchmark from the literature and showed a reduction in the number of transistors when compared to the baseline ESPRESSO.
Furthermore, a parameter sensitivity analysis is performed.
Thus, we propose here using the representation of CGP with the search procedure of a Clonal Selection Algorithm to minimize the number of transistors of combinational logic circuits. On the other hand, clonal selection techniques in general, and CLONALG in particular, were designed to avoid converging to a low-quality local optimum.
Despite the good results obtained by CGP techniques, its search procedure usually evolves a single candidate solution by an evolution strategy and this approach tends to be trapped in local optima. This procedure is called evolvable hardware and Cartesian Genetic Programming (CGP) is the evolutionary technique with the best performance in this context. Evolutionary techniques have been used in the design and optimization of combinational logic circuits.
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